The invention relates to the control of access to memory in a computer system.
A problem that the present invention addresses is the control of access to memory in a computer system in the event of an error related to one or more memory locations to be accessed. Accessing system memory can cause processor exceptions where, for example, a memory fails to respond to an access request, or data is returned that contains unrecoverable errors. Also, memory problems can cause bus errors on I/O buses supporting Direct Memory Access (DMA) by system devices other than the Central Processing Unit (CPU) of a processor.
Various approaches to resource access control have been proposed.
U.S. Pat. No. 5,627,965 describes a fault tolerant computer system including a central processor sub-system and a plurality of other subsystems, the subsystems being connected via a main data transfer bus. The central processor subsystem comprises three central processor modules. Each central processor module (or CPUset) includes a central processing unit (CPU) connected to a private bus, a first bus interface connecting the private bus to a shared bus, and a second bus interface connecting the shared bus to the main bus. The CPUsets are connected over respective private buses to a shared bus. Connected to the shared bus is a slot response memory. The slot response memory includes locations corresponding to respective slots for subsystems on the main bus. Accordingly to column 15 of U.S. Pat. No. 5,627,965, where a subsystem in a slot is functioning correctly, a location in the slot response memory corresponding to that slot will contain xe2x80x980xe2x80x99 data and the slot response register will not interfere with data transfers on the main bus. Where the subsystem in a slot becomes defective or absent from the system, then the location in the slot response memory corresponding to that slot is set to xe2x80x981xe2x80x99 and all subsequent attempts to access the defective or absent subsystem will result in artificial termination of the data transfer attempt.
PCT application PCT/US99/12605 is directed to a bridge for a fault tolerant computer system, which bridge connects I/O buses of first and second processing sets to a common I/O device bus. A resource control mechanism in the bridge provides an interface for exchanging signals with one or more resource slots of the device bus, each of the resource slots being capable of communicating with a system resource. The resource control mechanism in the bridge also includes a register associated with each system resource, the register having switchable indicia that indicate an operating state of the associated system resource. The control mechanism is operable in use to direct signals to and/or from respective system resources of the computer system.
The known systems provide for control of the access to a system resource in a slot on a bus by means of a control mechanism external to the processor. Such access control mechanisms can provide for the trapping of accesses to a faulty resource in a slot on a bus. However, they do not address specifically, the control of access to memory in a computer system in the event of an error related to one or more memory locations to be accessed. Repeated attempts to access a faulty memory location can cause multiple processor exceptions to occur, and in the case of direct memory access operations, can cause bus errors to occur.
An aim of the present invention is to provide a memory access controller, a memory subsystem, a computer system and a method of controlling memory access that addresses these problems associated with the control of access to memory.
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Combinations of features from the dependent claims may be combined with features of the independent claims as appropriate and not merely as explicitly set out in the claims.
In one aspect, the invention provides a memory controller for controlling access to one or more memory units. The memory controller includes access control logic operable to receive a memory access request that references at least one memory address. It further includes a fake response record operable to record a fake response indication for an address for which a response is to be faked. The access control logic is operable on receipt of a memory access request to access the fake response record and to fake a response where a fake response indication for an address indicates that a response is to be faked.
An embodiment of the invention is able to halt an attempt to access a faulty memory location and to fake a response to such an access attempt. Specifically, a memory controller in accordance with the invention provides a faked response for selected memory locations. By providing such a faked response, an embodiment of the invention is able avoid multiple exceptions occurring for the same memory location in a CPU. Only a first exception will occur on the first error, with subsequent accesses being stopped before they can cause a further exception. Similarly, by providing such a faked response, multiple bus errors for a memory location can also be avoided where a bus supports Direct Memory Access (DMA).
An address in a received memory access request can be compared to entries in the fake response record and, where a match is found, a faked response can be generated. Where the memory access request is a read request, fake data for the faked response can also be generated. The fake data can be retrieved from a fake data register. Alternatively, it can be retrieved from the fake response record.
In one embodiment, the fake response record is a table of memory locations for which a response is to be faked. The fake response record can identify blocks of memory locations for which a response is to be faked. The fake response record can be in the form, for example, of an associative table containing entries for memory addresses for which a response is to be faked.
The memory controller can be operable, on detecting a faulty memory location, to add the memory address for that location to the fake response record. Verification of faulty responses can be determined using conventional methods, for example parity and/or other checks.
Routing logic can be provided to connect the access control logic to at least one memory unit.
The memory controller can be integrated in an integrated circuit.
In another aspect, the invention provides a memory subsystem including at least one memory controller as set out above and at least one memory unit. At least one memory controller and at least one memory unit can be integrated in the same integrated circuit.
In a further aspect, the invention provides a computer system including a processor, a bus and a memory subsystem as set out above.
The processor can be operable, on detecting a faulty memory location, to cause the access control logic to add memory address for that location to the fake response record.
In yet a further aspect, the invention provides a method of controlling memory access by a memory controller. The method includes receiving, at a memory controller, a memory access request that references at least one memory address; accessing a fake response record to determine whether a response for at least one memory for the access is to be faked; and if the response is to be faked, returning a faked response.